In many integrated circuit packages, it is desirable to provide a reference clock signal (also commonly referred to as a system clock). Many devices use the reference clock signal to derive their respective timing. For example, a reference clock signal may be provided to memory devices, processors, or other circuitry located on an integrated circuit (or chip).
Often, it is desirable to delay the reference clock signal in a manner that creates multiple iterations of the clock signal. These multiple iterations of the reference clock are separated by a known period of time, which is commonly referred to as phase. For example, a known way of creating multiple iterations of a reference clock is to supply the reference clock to a delay locked loop (DLL). A DLL, as known in the art, is a device that takes the reference clock signal and passes the signal through one or multiple delay lines connected in series. With multiple delay lines connected in series, each delay line supplies a subsequent delay, such that multiple iterations of the reference clock signal appear at different times, and such that the total delay in the chain is equal to a single clock period under all PVT condition.
Programmable delay lines are required for the generation of accurately shaped waveforms, and for delaying electronic signals. These waveforms are used in automated test systems (ATEs), to measure time intervals and to sample data at circuit interfaces.
Specific applications require varying degrees of accuracy and resolution in the delay of the electronic signal. ATEs can require delay lines with a delay resolution of 10 to 20 picoseconds. Data sampling of circuit interfaces may, for example, only require delay lines with delay resolutions of 100 to 200 picoseconds for systems operating at 100 MHz. Strobe signals in high speed interfaces require delay lines in which the delay remains constant even though the delay line may be fabricated using varying process corners, and the delay line is subjected to varying temperatures and supply voltages.
Programmable delay lines have been designed using random access memory (RAM), coupled oscillators, shift registers, charge coupled devices (CCDs), ramp comparators, multiplexed delay lines and tapped delay lines. Each of these types of delay line designs suffers limitations. These limitations include the resolution of the delay of the delay line being too coarse, or the delay of the delay line being inconsistent. Delay inconsistencies can be due to variations in the process used to fabricate the delay line, or variations in the delay of the delay line due to variations in the temperature or voltage supply of the delay line.
In clock generation applications, an input clock signal is provided. However, a particular application may require different phases of the input clock signal. The clock generation application receives the input clock signal and based thereon generates a plurality of phases of the input clock signal.
U.S. Pat. No. 5,900,762, entitled, “Self-calibrating Electronic Programmable Delay Line Utilizing an Interpolation Algorithm,” describes an example of a prior art programmable delay line.
One manner in which to generate phases of an input clock signal is to employ delay cells. For example, a delay chain that includes a plurality of delay taps, where each tap provides one of the phases of the input clock signal, is often utilized for clock signal generation. Each tap includes a plurality of delay cells. Each delay cell typically includes inverters and transmission gates for directing a signal along one of two data paths. Each delay cell can receive control signals for selecting the data path.
In order to insert a long delay the signal is sent in a forward direction for a long time and then one of the delay cells along the path is turned on in order to direct the signal along a return path.
The delay chain is typically designed for a particular clock frequency (e.g., 70 MHz). The frequency of the clock signal specifies the period of a cycle of the clock signal. As can be appreciated, for high frequency clock signals, the period is smaller as compared with the period of a lower frequency clock signal. Each delay cell is designed to meet a particular frequency and the smallest delay corresponding to the smallest phase shift required by a particular application.
As can be appreciated, it is desirable for there to be a delay cell design that can accommodate a range of frequencies. Unfortunately, in order to accommodate high frequency clock signals, the delay cells must feature a very small delay. However, when a lower frequency clock signal is encountered, many delay cells must be stacked (e.g., configured in a daisy chain) in order to feature a larger delay required by the slower frequency clock signal.
Another disadvantage of prior approaches is that the design often includes a plurality of parasitic capacitive elements in the signal path. In these schemes, it is difficult to optimize the design of any one element since optimizing one element tends to diminish the performance of other elements in the signal path. Accordingly, it is desirable for there to be a delay cell design that reduces the number of elements in the signal path and simplifies the optimization of components in the delay cell.
In other words, each delay cell is designed for a minimum resolution for the fastest clock. In order to meet the slowest clock and other slower clock frequencies, additional delay cells are stacked. In this manner, each tap (plurality of delay cells) provides a fixed incremental delay.
One difficulty with this approach is that the percentage of the fast clock is smaller than the same percentage of a slower clock (i.e., since the period of the fast clock is less than period of the slower clock, the same percentage of the period of the slower clock is larger than the period of the fast clock). The effect is that more delay elements are needed to handle the slower clock's period. The use of delay elements having a single resolution is inefficient, since a slower clock can have a larger delay. Unfortunately, the additional delay elements occupy more area, thereby increasing the cost of the part incorporating such a design.
Consequently, it is desirable for there to be a delay element that has a variable incremental delay.
It is also desirable for there to be a delay cell that can accommodate clock signals with a range of frequency values.
Another difficulty encountered by the prior art delay cell designs is that any errors in the design of the delay cell is compounded many times since there are typically seven to twenty delay cells per tap and 32 or 64 taps per delay chain. In this regard, it is desirable to reduce the number of delay cells utilized in a delay chain.
Based on the foregoing, there remains a need for a balanced programmable delay element that overcomes the disadvantages set forth previously.